While searching for a way to take logs on an FPGA (without resorting to the sledgehammer of CORDIC) I stumbled upon Micheal Dunn’s Single-cycle logarithms & antilogs article in EDN. His method is a clever extention of the mathematician’s approximation: to take the log (base 10), just count the digits. In binary we can get the log (base 2) by “counting the digits” with a priority encoder—which outputs the position of the highest nonzero bit.
This bit-counting is pretty cheap, and gives us the integer part of the log. Next is is the clever bit: we can get the fractional part by left-aligning the input with a barrel shifter (by left shifting the input by the binary not of the integer part) then feeding that into a LUT (???). How on earth that works (and besides… what goes in the LUT?) is what I want to analyse here, as it falls quite neatly out of some algebra.
(TODO: add diagram here)
To work out the behaviour mathematically, first consider the priority encoder output
We can now write the equation for the output of the barrel shifter
As left-shifting is exponentiation, we have:
We can substitute in
This is why we had to bitwise not
This gives us the equation for the fractional part
At first glance it looks like we’re right back where we started, as we have to take the log of
Recall that
// TODO
As a sanity check, substitute the definition of
Which is exactly the definition of